Two basic functions of any asynchronous transfer mode switch are contention resolution and buffering of contending cells. In ATM switching architectures, no attempt is made to find a time slot for an arriving cell that is mutually convenient to the inlet and outlet where the cell is to be switched. Thus, output contention will necessarily occur among cells arriving simultaneously for the same destination. Discarding cells that cannot be delivered due to output contention is not acceptable; therefore, buffering must be provided for the contending cells.
The two most distinct characteristics of any ATM switch are the location of the buffers and the means for identifying and resolving output contentions among cells. Many architecture that have been devised suffer from drawbacks in operation. For example, an input buffer architecture has limited throughput, performs multicasting with difficulty, and requires a global contention resolution tournament that makes expansion highly complex. In output buffer architectures, high performance and complex queuing disciplines are not easily achieved. A hybrid input/output buffer architecture resolves some performance limitations of the above designs but adds additional hardware complexity and does little to improve multicasting implementation. In shared memory architectures on the other hand, memory access bottlenecks occur and implementation complexities increase. Therefore, it is desirable to have an ATM switching architecture with an improved buffering technique, multicasting capabilities, a contention resolution tournament that is easily expandable, and improve results in reduction of cell discarding.
From the foregoing, it may be appreciated that a need has arisen for an ATM switching architecture that has an improved contention resolution tournament for identifying and resolving output contentions among incoming cells. A need has also arisen for an improved buffering discipline that stores contending cells and reduces the possibility of cell discarding. Further, a need has arisen for an ATM switching architecture that can effectively discriminate between segments of classes of service with different switching delay requirements, and that can measure the switching delay experienced by each class of service and can modify it dynamically to meet the expected switching delay performance of each class.